Integrated half-bridge power circuit

ABSTRACT

A down converter includes an integrated circuit, which includes a control FET (CF) and a synchronous rectifier FET (SF). The control FET is a lateral double-diffused (LDMOS) FET, and the conductivity-type of the LDMOS FET and the conductivity-type of the substrate are of the same type.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the benefit of U.S. provisional application Ser.No. 60/432,302 filed Dec. 10, 2002, which is incorporated herein byreference.

The present invention relates generally to integrated power conversioncircuits using a half bridge, and particularly, to integratedpower-transistors for a down-converter power supply having improvedswitching characteristics.

Power-converters are often used in power supplies, power amplifiers andmotor drives. Down converters, including Buck converters are often usedto convert an input voltage to a lower voltage for supplying power to aload, such as a microprocessor. These microprocessors have applicabilityin personal computers (PC) as well as other electronic devices. In PCapplications, the input voltage to the converter is on the order of 12V, and the required output is on the order of approximately 1.4 V, or afactor of about ten in step-down. Moreover, the required output currentsof these converters are increasing to above 50 A, further adding to thedesign considerations of these circuits, and their devices.

Down-converter circuits often include a control transistor and asynchronous rectifier. These devices are often metal-oxide-semiconductor(MOS) transistors, which are silicon-based field effect transistors(FET). The use of a control FET (CF) and a synchronous rectifier FET(SF) has certain advantages. However, in known circuits these devicesare discrete elements or are disposed in modules. Such circuits havecertain drawbacks. For example, as the demand for faster switchingfrequencies increases, parasitic effects in such devices can have adeleterious impact on the ability of the CF and SF to meet thesedemands.

The losses associated with the on-and-off switching of down convertersare beneficially minimized as much as possible. This has certainbenefits, such as improving the battery life within the PC and reductionof the heat-dissipation. Conversion loss in MOSFET's is determinedpartly by resistance and partly by the figure of merit of the device,which is proportional to the on resistance, R_(on) and the gate-to-draincharge, Q_(gd).

In accordance with an exemplary embodiment of the present invention, adown converter comprises an integrated circuit having a control FET (CF)and a synchronous rectifier FET (SF), wherein the control FET is alateral double-diffused (LDMOS) FET, and the conductivity-type of theLDMOS FET and the conductivity-type of the substrate are the same.

As will become clearer as the present description continues, theon-resistance and the gate-to-rain charge are improved via exemplaryembodiments described herein. Other benefits of the embodiments arereduced parasitics, an option for integration of interface circuitry(for better control of the power-device switching) and a reducedproduction cost.

The invention is best understood from the following detailed descriptionwhen read with the accompanying drawing figures. It is emphasized thatthe various features are not necessarily drawn to scale. In fact, thedimensions may be arbitrarily increased or decreased for clarity ofdiscussion.

FIG. 1 is a schematic diagram of a down converter in accordance with anexemplary embodiment of the present invention.

FIG. 2 a is a cross-sectional view of the integrated CF and SF used in adown converter in accordance with an exemplary embodiment of the presentinvention.

FIG. 2 b is a cross-sectional view showing a plurality of conductiveplugs inside the cells (source/drain fingers) of a CF-switch of adown-converter in accordance with an exemplary embodiment of the presentinvention.

FIG. 3 is a cross-sectional view of the integrated CF and SF used in adown converter in accordance with an exemplary embodiment of the presentinvention.

FIG. 4 is a cross-sectional view of the integrated CF and SF used in adown converter in accordance with an exemplary embodiment of the presentinvention.

FIG. 5 is a cross-sectional view of the integrated CF and SF used in adown converter in accordance with an exemplary embodiment of the presentinvention.

In the following detailed description, for purposes of explanation andnot limitation, exemplary embodiments disclosing specific details areset forth in order to provide a thorough understanding of the presentinvention. However, it will be apparent to one having ordinary skill inthe art having had the benefit of the present disclosure, that thepresent invention may be practiced in other embodiments that depart fromthe specific details disclosed herein. Moreover, descriptions ofwell-known devices, methods and materials may be omitted so as to notobscure the description of the present invention.

FIG. 1 shows a down converter circuit 100 in accordance with anexemplary embodiment of the present invention. The circuit 100 isillustratively a Buck-converter circuit with a CF 101 and an SF 102. Theinput voltage, which is illustratively on the order of approximately12V, is from a voltage source or power supply (not shown), and isapplied over input terminals 103 and 104. The output terminals 105 and106 are connected to an inductor 107, and ground, respectively. The loadis a large storage capacitor 108 and a resistor 109. The resistor 109represents one of a variety of electronic devices connected to thedown-converter 100. For example, the resistor 109 may be amicroprocessor. It is noted, however, that the use of the down convertercircuit 100 of the exemplary embodiment is not limited to amicroprocessor-based applications. For example, the converter-circuitmay be used in switch-mode (audio) amplifiers. Still other applicationsof the converter circuit 100 will become apparent to one skilled in theart having had the benefit of the present disclosure.

Generally, the requirements on down converters such as circuit 100 areto provide an increasingly lower output voltage at the load, whileproviding an increasing current to the load. These requirements arecoupled with a requirement for very low-ohmic switches. Furthermore, areduction of the physical sizes and values of the inductor 107 and ofthe capacitor 108 (typically on the order of several mF) is desired incompact high-speed down-converter applications (e.g., on the order ofapproximately 300 kHz to approximately 2 MHz, with transients on theorder of nano-seconds), and requires faster on/off switching-time ofcurrent to the load. Notwithstanding the need for efficient and rapidsupply of the power to the load, the down converter circuit 100 usefullyhas reduced electronic parasitics.

As is known, in efficient high-speed power devices and circuits, thegreatest sources of parasitic effects are parasitic resistance andinductance, which deteriorates the efficiency and switching speed of adevice. Therefore, it is useful to reduce all parasitics (resistive andinductive) in the total switching path (e.g., the transistor, thetransmission lines, the packaging, etc.) As will become clearer as thepresent description proceeds, these parasitics are reduced viaintegrated circuits of exemplary embodiments described herein.

The exemplary embodiments include integration of the CF 101 and the SF102 in a semiconductor device structure (chip) that reduces theundesirable electronic parasitics by various methods and structures.Moreover, these embodiments foster the fabrication of the CF 101 and SF102 in an integrated package or directly on the circuit board of theload (e.g., PC-board in a microprocessor application) using a minimumnumber of processing steps, so the overall cost of the device iscomparatively reduced through a reduction in processing complexity.Finally, in addition to reducing the parasitic resistance and inductancethrough transistor choice and design, the exemplary embodiments reducethe spacing between the transistors to realize a reduction in theparasitics.

FIG. 2 a shows an integrated circuit (IC) 200 in accordance with anexemplary embodiment of the present invention. It is noted that thevarious materials and doping polarities are intended to be illustrativeof the exemplary embodiments. Clearly, other materials, elements anddoping polarities may be used to realize the exemplary embodiments.Moreover, it is noted that known materials and semiconductor processingtechniques may be used to realize the IC 200. As such, in the interestof brevity and clarity of the description of the exemplary embodiments,these known materials and techniques are generally omitted.

The IC 200 is illustratively a half-bridge circuit and includes devicesfabricated on a common n⁺ substrate 201, which is illustratively n-dopedsilicon. A vertical double-diffused MOS (VDMOS) transistor 202 includesa gate 219 having a gate contact 205, a drain contact 223, an n+ source216 and a p-body 218 shorted to the source 216 via source contact 203.The VDMOS is formed in an n-doped epitaxial (epi) well 206. The drain ofthe VDMOS structure is comprised of a heavily doped (n⁺) drain 204 andthe n-epi well 206. Hereinafter the VDMOS drain will be referred to asdrain 204.

In the present exemplary embodiment, the VDMOS transistor 202 isconfigured to function as the SF rectifier 102 of the down convertercircuit 100 as will become clearer as the present description continues.Beneficially, the VDMOS FET 202 is a trench-gate structure, whichgenerally provides a lower on-state resistance (for example, on theorder of 10 mOhm*mm² for a device with an operating voltage ofapproximately 25 V) compared to other FET devices.

An LDMOS transistor 207 is formed in a buried p-well 221, and includes agate 211; an n+ source 214 shorted to a p-body 217; and an n− drain 215,which is formed in an n-type well 220. The gate contacts 205 and 211 areeach connected to a control section (not shown) that drives the gates219 and 211 for switching the FET's 202 and 207 on and off. In theexemplary embodiment, the LDMOS FET functions as the CF of thedown-converter circuit 100.

The IC 200 may also include an NMOS FET 226 and a PMOS FET 227, whichmay be used in various applications of the IC. The FET's may be used inconjunction with interface circuitry (not shown) for better control ofthe switching, and a reduced inductance in the gate-drive circuit. Theseand other devices may also be incorporated on the IC in keeping with theexemplary embodiments.

Illustratively, gate 219 is driven between ground and approximately 5Vto approximately 12 V. Gate 211 is driven between the gate voltage andsource voltage of the LDMOS FET 207. The source contact 208 connects thesource 214 to the output 208 and the drain 204, which cycles betweeninput-voltage (approximately 12V) and a flyback-voltage (typically about−0.2V). Hence, the gate 211 is driven by a control block supplied by anexternal capacitor, which is illustratively charged by a bootstrapcircuit and/or a charge-pump circuit (not shown).

As mentioned above, it is useful to provide circuit 100 including thepower transistors (FET'S) with a reduced parasitic inductance andon-resistance compared to known devices. Illustratively, by virtue ofthe IC 200, the parasitic inductance of the circuit 100 including thehalf-bridge IC 200 of an exemplary embodiment is on the order ofapproximately 1.0 nH, while the on-resistance is on the order ofapproximately 5 mOhms to approximately 10 mOhms. The reduced parasiticinductance results in an improved switching speed (on/off time) for theload (e.g., capacitor 108 and resistor 109), while the reducedon-resistance results in a reduction of the conductive losses of the IC.

The semiconductor device structure and design of the IC 200 realizesbenefits in reduced parasitics in part because of the reduced parasiticsof the devices that comprise the IC 200. For purposes of illustration,the VDMOS FET 202 provides a relatively low on-state resistance,illustratively on the order 10 mOhm*mm² for a 25V device and areasonable Q_(gd). The LDMOS FET 207 also provides a reasonable lowon-resistance (illustratively 25 mOhm*mm² for a 25V device), and a lowQ_(gd).; the product (Ron*Qgd) is illustratively on the order ofapproximately 12 mOhm*nC for LDMOS FET 207. Of course this is merelyillustrative, and other similar improved values may be realized via theexemplary embodiments depending on the application.

In the exemplary embodiment shown in FIG. 2 a, the drain contact 209 isconnected to the voltage input of the down-converter circuit 100 (e.g.,12V as mentioned above), while the source contact 208 is connected tothe drain contact 223 of the VDMOS FET, which is also the drain of theSF 102 in the present exemplary embodiment The source contact 208 isillustratively connected via a deep connection such as a conductive n+plug 210 (or heavily doped sinker) in the substrate 201. Alternatively,an n+ plug 210 may be disposed in an etched trench or dip; or a metalshort (or via) may be disposed in an etched trench to achieve this end.In any event, this provides a low-Ohmic connection with a small lateraldimension. The conductive plug 210 or similar device then is applied onmultiple locations inside a cell of LDMOS devices, (e.g., as shown inFIG. 2 b) thus connecting source-contact 208 with low resistance toheavily doped drain 204, using contact 222 with a relatively thin firstmetal only, which allows fine patterns inside the cell. This isadvantageous for allowing a thick (second) power-metal for 203 and 209on the top-side of the IC with coarse patterns and a thick power-metal(drain contact 223) for the output at the bottom-side (i.e., beneath thesubstrate).

As can be appreciated, the source contact 208 of the LDMOS FET 202 andthe drain contact 223 of the VDMOS FET 207 have now a low-ohmicconnection on the chip (IC) and are connected to an inductor of a downconverter, such as inductor 107 of FIG. 1. Beneficially, this fosters areduction in parasitics compared with other structures. Finally, otherconnections are made in a relatively straightforward manner, so the IC200 is connected to the other elements of the down converter circuit100.

The IC 200 is fabricated illustratively as follows, using well-knownsemiconductor processing techniques. An n+ silicon layer forms thesubstrate 201, with n− epitaxy approximately 3-4 um in thickness formingthe n− well 206. This epi-layer is about 2-3 um in thickness at end ofprocessing. This step is followed first by a P-well implantation anddiffusion to form the p-well 221 and p-wells 224 and 225 of the NMOS andPMOS FET's 226 and 227, respectively. An N-well implantation is carriedout to form the n-wells 220 of the LDMOS drift-region and the PMOS FETn-well 228. This is followed by a dopant diffusion. A deep n+ plug 210may then be implanted if desired, followed by a diffusion. Thereafter atrench is etched for the VDMOS FET 202.

Alternatively, the deep N-type plug 210 could be fabricated using thetrench with additional n+ implant in its bottom for a surface contact tothe n+ wafer to form the drain contact 204. Next an optional field-oxidestep is carried out via local oxidation of silicon (LOCOS). Thisfield-oxide (not shown) also may be grown, or deposited and etched.Thereafter, a gate-oxide formation (e.g., by oxide growth) step iscarried out to form the gate oxides of the VDMOS FET 202 and LDMOS FET207. These gate oxides have a thickness of approximately 15 toapproximately 40 nm, depending on the required gate-source voltage(Vgs), which is illustratively approximately 5V to approximately 12V.

Thereafter, a poly-silicon deposition and n+ doping is carried out,which is followed by patterning of the poly. After the poly-depositionsequence is complete, a shallow p-type DMOS body-implantation iseffected to form the body 218 (e.g., with Latid-Boron, with Arseniclink). Next, a (oxide) spacer (not shown) is formed by standardprocessing techniques. This processing sequence results a short-channeland a good link to the source, which fosters a low-R_(on) for the LDMOSFET 207. Next, a shallow n+ region, and a shallow p+ region areimplanted and activated, followed by field-oxide (FOX) deposition,contact-windows (not shown), first metal, oxide or nitride-deposition,vias (not shown), thick second metal (not shown) with a seed-layer andgalvanic copper 10-15 um, covered by protection and opened to bond-pads(not shown).

In operation, if the LDMOS FET 207 (CF) is on, it charges the n+substrate to the input voltage (e.g., 12V), thereby providing a currentin the load-inductance 107. If CF is closed, the load-inductance 107pulls the n+ substrate from 12V towards approximately −0.1V or toapproximately −0.7V, depending on the turn-on timing of the VDMOS FET202. The current in a down-converter normally flows through theload-inductance 107 from the source 214 and to the load. Hence, thepotential on n+ substrate will not be above +12V; the potential on 209may rise above this value, depending on the inductance. Finally, it isnoted that in embodiments described herein, the inductance may bereduced further using surface solder-bumps and flip-chip packaging.

FIG. 3 shows an IC 300 in accordance with another exemplary embodimentof the present invention. This IC 300 shares common features andmaterials with the IC 200 previously described. As such, differenceswill be highlighted, and commonalities not discussed. The IC 300illustratively includes an n-type substrate 301 with two LDMOS FET's 302and 303, respectively. The LDMOS FET 302 is usefully the SF 102 of FIG.1, while the LDMOS FET 303 is the CF 101. The LDMOS FET 303 issubstantially identical to that described in FIG. 2 a. One differencelies in its source connection, which is via metallization connected tothe drain contact 304 of the LDMOS FET 302. This corresponds, of course,to the output 105 of FIG. 1.

The LDMOS FET 302, which functions as the SF 102, has a source 306 andbody 307 connected to ground via a source contact 308. The gate 309 isconnected to a control function (not shown) much like the controlfunction of the gate 211 described above. The drain 215 is placed in ann-well 220 and connected to output 304 via 305. The device is placed inan n-epi well 206. Advantageously, the IC 300 has a low on resistance,with each LDMOS transistor having an on-resistance (R_(on)) per unitarea on the order of approximately 10 mΩ*mm² for a 20V. Moreover, allpower connections to the IC are now on a common side of the chip,eliminating the need for the formation of backside contacts or the deepconductive plug(s) or similar device. This illustrative embodiment isalso beneficial because the substrate does not need to be thinned duringprocessing to reduce parasitic resistance, or to have a very lowresistivity via super-doping. This embodiment however puts higherdemands to the metallization of both LDMOS-devices, and may require anadditional (third) metal-layer and via-pattern.

FIG. 4 shows another exemplary embodiment of the present invention. Thisembodiment shares common features and structures with that of FIGS. 2 a,2 b and 3, and may be used in a circuit such as is shown in FIG. 1. TheIC 400 of FIG. 4 is essentially IC 300 with n+ plugs 401 (diffused,pre-etched or trench) and the n+ substrate 201 with output 105 of thecircuit of FIG. 1 at the bottom-side via metallization 223. Plugs 401are useful to relieve the demand on the metallization of both LDMOS FETsand allow for a two-layer metal-system, which is advantageous duringfabrication.

FIG. 5 is another exemplary embodiment of the present invention. Again,the IC 500 shares common features and structures with the exemplaryembodiments of FIGS. 2-4. To wit, IC 500 is essentially IC 400 except afrom p-epitaxial layer 501 is disposed on the n+ substrate 201; or maybe an n-epi layer on the n+ substrate 202 with a blanket P-wellimplantation and diffusion. Here device 309 is placed in a p-well 501.The plugs 401 also act for well-isolation in this embodiment. This savesat least one mask-step.

The invention being thus described, it would be obvious that the samemay be varied in many ways by one of ordinary skill in the art havinghad the benefit of the present disclosure. Such variations are notregarded as a departure from the spirit and scope of the invention, andsuch modifications as would be obvious to one skilled in the art areintended to be included within the scope of the following claims andtheir legal equivalents.

1. A down converter, comprising: an integrated circuit having a controlField Effect Transistor (FET) (CF) disposed in a first well having afirst polarity; and a synchronous rectifier FET (SF) having a sourceregion and a channel region both disposed in a second well having asecond polarity opposite the first polarity, wherein the control FET isa Lateral Double-Diffused Metal Oxide Semiconductor (LDMOS) type and theSF is a vertical Metal Oxide Semiconductor type; the first and secondwells are formed in contact with a heavily doped region of a substrate;and a conductivity- type of the LDMOS FET and a conductivity-type of theheavily doped region of the substrate are of the same type; wherein atleast a portion of the heavily doped region forms a drain region for theSF; and a source contact of the CF is connected to drain region of theSF via a conductive plug in the substrate.
 2. A down converter asrecited in claim 1, wherein the synchronous rectifier FET is a VerticalDouble-Diffused Metal Oxide Semiconductor (VDMOS) FET.
 3. A downconverter as recited in claim 1, wherein the synchronous rectifier FETis a vertical trench DMOS FET.
 4. A down converter as recited in claim1, wherein the integrated circuit does not include isolation regionsbetween the CF and the SF.
 5. A down converter as recited in claim 1,wherein the conductivity type of the heavily doped region is n-type. 6.A down converter as recited in claim 1, wherein the integrated circuitfurther includes one or more additional FETs configured to control gateswitching of the control FET and the synchronous rectifier FET.
 7. Adown converter as recited in claim 1 further comprising an inductor,wherein the source contact of the control FET and a drain contact of thesynchronous rectifier FET are connected to the inductor of the downconverter.
 8. A down converter as recited in claim 1 further comprisingan inductor, wherein the source contact of the control FET and a draincontact of the synchronous rectifier FET are connected to the inductorof the down converter, the conductive plug forms a low-ohmic connectionto mitigate resistive and inductive parasitics of the integratedcircuit.
 9. A down converter as recited in claim 8, wherein theintegrated circuit has a parasitic inductance on the order of 1 nH orless.
 10. A down converter as recited in claim 1 further including avoltage input, wherein the control FET has a drain contact connected tothe voltage input of the down converter.
 11. A down converter as recitedin claim 10, wherein the source contact of the control FET is connectedto the drain contact of the synchronous rectifier FET via the conductiveplug and a portion of the heavily doped region in the substrate.
 12. Adown converter as recited in claim 1 wherein the control FET includes agate driven by a control block supplied by an external capacitor.